Design of Phase Shifted Sine Wave Generator Based on DSP Digital Oscillator

0 Introduction

There are many methods to generate digital phase-shifting signal. The traditional phase-shifting principle of direct digital frequency synthesis (DDS) is to digitize the sine wave signal, form a data table and store it in two ROM chips, and then pass through two chips. The D / a conversion chip can obtain two sine wave signals by continuously outputting the data table under the control of the counter. When the data sequences obtained by two D / a conversion chips are identical, the two sine wave signals obtained by conversion have no phase difference. When the data sequences obtained by two D / a conversion chips are different, there is a phase difference between the two sine wave signals obtained by conversion. The value of phase difference is related to the total number of data in the data table and the offset of data address. The essence of this processing method is to map the offset of data address into the phase value between signals. The deviation of the data can be obtained by an external microprocessor. This value corresponds to the phase shift angle of the sinusoidal signal. The direct frequency synthesis method has the advantages of short frequency conversion time, good phase noise performance, high precision and wide frequency range of the generated signal. However, due to the need to use address, phase calculation, access memory operation and other links, the direct frequency synthesizer has complex structure, high cost and low phase-shift resolution. In this paper, two sine wave signals are obtained by using DSP technology and numerical iteration method, that is, using the implementation principle of DSP digital oscillator. Through simulation and hardware implementation, two sine wave outputs with set parameters can be obtained, which achieves the design purpose, and has the characteristics of convenient and flexible adjustment and high resolution. The numerical iteration method can accurately calculate the sinusoidal value of the angle, only need a small storage space, select the number of samples in the sinusoidal cycle and change the delay between samples, which can produce waveforms with different frequencies. The waveform amplitude and phase can be changed by software.

1. DSP implementation principle of waveform and phase-shifting waveform generator

Using DSP to generate sinusoidal signal through operation and iterative method, that is, digital oscillator. The unit impulse response of the digital oscillator is sin (n) ω T θ)· U (n) is the system in δ (n) Under the excitation of, oscillation is generated, and the output phase is θ The system function of the system is the z-transform of the impact response, i.e

Then the corresponding difference equation of the system is

By iteration, the shock response of the system can be obtained from the difference equation. The input of the system is x (n)= δ (n) , the initial condition is zero. Then from the difference equation:

When n ≥ 3, there is: Y (n) = 2cos ω T · y (n-1) - Y (n-2). After n ≥ 3, y (n) can be calculated by Y (n-1) and Y (n-2), which is a recursive difference equation. Therefore, the following conclusion is obtained: as long as the angular frequency of the system output sinusoidal signal is known ω And sampling period T to obtain the system difference equation. The system only needs to calculate the difference equation every T seconds to obtain the value of current sinusoidal sampling sequence y (n). Set Y (1), y (2) In the design, the main program inputs data such as frequency and phase difference through the keyboard. During initialization, the initial values Y1 (1), Y1 (2) and Y2 (1) Y2 (2) of the two sinusoidal signals are calculated according to the output signal frequency, sampling rate and phase difference , and then open the timer interrupt. Each time you enter the timer interrupt service program in the future, use the previous Y1 (1), Y1 (2) and Y2 (1) Y2 (2) to calculate the new Y1 (0) and Y2 (0). Although there is a certain delay in twice calculating and outputting Y1 (0) and Y2 (0), the error will be very small due to the high-speed pipeline operation of DSP and the high-speed serial output of McBSP.

2 system hardware implementation scheme

The system structure of two output phase shifted sine waves based on TMS320VC5416 DSP is shown in Figure 1. The central processing unit of the system adopts American Ti (Texas Instruments) The company's high-performance fixed-point digital signal processing chips TMS320VC5416 and TMS320 vc54.16 are a low-power and high-performance fixed-point digital signal processor specially designed for portable devices by TI company. Compared with other C54 series processors, the running speed reaches 160mpis, the on-chip RAM reaches 128K, and the program addressable space reaches 8m, which provides rich conditions for a large number of data processing In particular, vc5416 provides a variety of on-chip and external resources; software programmable wait state generator, programmable PLL clock generator, 1 16 bit timer, 6-channel direct memory access controller (DMA), 3 multi-channel buffered serial ports (McBSP) In addition, TMS320VC5416 supports mixed programming of C and assembly language. Efficient pipeline operation and flexible addressing mode make it especially suitable for high-speed real-time signal processing. Because the system has two sinusoidal signal outputs, the system adopts two signal time-sharing transmission mode. TLC320AD50C is a piece produced by TI company, which integrates a / D and D / a conversion functions The analog interface chip adopts sigma delta technology to realize high-precision A / D and D / a conversion at low system cost. The chip is composed of a pair of 16 b synchronous serial conversion channels. There is a decimation filter after ADC and an interpolation filter before DAC. TLC320AD50C supports master-slave two working modes, and supports up to three slaves. Using this feature, the system will The two tlc320ad50cs are connected in series, so that one is the master device and the other is the slave device. The serial communication with the two tlc320ad50cs is realized through the multi-channel buffer serial port McBSP of TMS320VC5416. Tms320vc54.16 controls the two tlc320ad50cs to transmit data to the two tlc320ad50cs in time division multiplexing mode for D / a conversion output. The M / s of ad50c1 is connected to high level and the M / s of ad50c2 is connected to low level The XF pin of vc5416 is used to provide primary and secondary communication selection signals for ad50c. Tlc320ad50 is widely used in audio data acquisition and processing. It can be seamlessly connected with the McBSP of tms320c54xdsp for data acquisition, storage and processing. SCLK output clock, DIN serial input, dout serial output, FS frame synchronization signal output, corresponding to the corresponding pins of DSP. McBSP has Features: ① for the reception of serial port, the transmission clock can be provided by both external equipment and internal clock generator; ② the polarity of frame synchronization signal and data clock signal can be programmed, and the internal clock and frame signal generator can also be controlled by software programming; ③ the signal transmission and reception part of serial port can not only operate separately, but also work together; ④ interrupt signal of CPU The synchronization signal of No. 1 and DMA makes the McBSP serial port run under the control of CPU, and can also run independently without CPU and directly access the memory through DMA; ⑤ the multi-channel selection part makes the serial port have the communication ability of multi-channel signals, and its multi-channel receiving and transmitting ability can reach 128 channels; ⑥ the data width can be arbitrarily selected from 8b, 12b, 16b, 20b, 24b and 32B, and the data can be selected A-Law and u-law compression and expansion. McBSP serial port includes a data channel and a control channel. The data channel completes the transmission and reception of data. McBSP sends data through DX pin and receives data through Dr pin. The tasks completed by the control channel include the generation of internal clock, the generation of frame synchronization signals, the control of these signals and the selection of multiple channels. The control channel is also responsible for The generated interrupt signal is sent to the CPU to generate a synchronization event signal to notify the DMA controller. The control information is transmitted in the form of clock and frame synchronization signal through the control channel.

3 system software design and CCS simulation results

The system software is mainly composed of several modules, such as BootLoader download program, system initialization, keyboard display, timing interrupt processing and so on. When the system starts to power, it executes BootLoader program first, and executes the target program from the external FLASH to the RAM in the chip.

The system initialization program completes the initialization settings of each control register of TMS320VC5416, McBSP serial port control register, timer and corresponding registers of TLC320AD50C. The flow chart of main program and timing interrupt service program is shown in Figure 2.

CCS simulation waveform with sine wave frequency of 2 kHz, sampling frequency of 40 kHz and phase shift of 60 degrees is shown in Figure 3.

4 Conclusion

This paper presents a design method of generating phase-shifting sine wave based on DSP digital oscillator. The experimental results show that the system has stable waveform, strong anti-interference ability, convenient adjustment of frequency, phase and amplitude, high precision, output frequency range of 20 Hz 20 kHz, phase shift of 0 360 °, phase-shifting resolution of 0.001 degrees. In addition, if the system is connected with high-speed DA conversion chip, it can be large The design scheme is simple, feasible, novel and practical, and has the value of popularization and application.

Design of Phase Shifted Sine Wave Generator Based on DSP Digital Oscillator 1

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